VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects

As VLSI technology continues to scale, parameter variation is about to pose a major challenge to high-performance processor design. In particular, within-die variation is directly detrimental to a processor’s frequency and leakage power. To gain an understanding of this problem, this paper starts out by proposing a microarchitecture-aware model for parameter variation. It includes both random and systematic effects. It is partially calibrated with empirical data and uses a few intuitive parameters. Then, we extend the framework to model timing errors caused by parameter variation. This model yields the failure rate of microarchitectural blocks as a function of frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.